? semiconductor components industries, llc, 2006 june, 2006 ? rev. 6 1 publication order number: mc14549b/d mc14549b, mc14559b successive approximation registers the mc14549b and mc14559b successive approximation registers are 8?bit registers providing all the digital control and storage necessary for successive approximation analog?to?digital conversion systems. these parts differ in only one control input. the master reset (mr) on the mc14549b is required in the cascaded mode when more than 8 bits are desired. the feed forward (ff) of the mc14559b is used for register shortening where end?of?conversion (eoc) is required after less than eight cycles. applications for the mc14549b and mc14559b include analog?to?digital conversion, with serial and parallel outputs. features ? totally synchronous operation ? all outputs buffered ? single supply operation ? serial output ? retriggerable ? compatible with a variety of digital and analog systems such as the mc1408 8?bit d/a converter ? all control inputs positive?edge triggered ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving 2 low?power ttl loads, 1 low?power schottky ttl load or 2 htl loads over the rated temperature range ? chip complexity: 488 fets or 122 equivalent gates ? pb?free packages are available* maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ?0.5 to +18.0 v input voltage range, all inputs v in ?0.5 to v dd + 0.5 v dc input current per pin i in 10 ma power dissipation per package (note 1) p d 500 mw operating temperature range t a ?55 to +125 c storage temperature range t stg ?65 to +150 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c this device contains protection circui try to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. x = 4 or 5 a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package marking diagrams http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ordering information pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q0 q1 q2 q3 v dd sc * eoc q7 q6 q5 q4 v ss c d s out *for mc14549b pin 10 is mr input. for mc14559b pin 10 is ff input. pdip?16 p suffix case 648 16 1 mc145x9bcp awlyywwg 1 1 so?16w dw suffix case 751g 16 1 mc145x9b awlyywwg
mc14549b, mc14559b http://onsemi.com 2 sc sc( t?1 ) mr mr( t?1 ) clock action x x x x none x x 1 x reset 1 0 0 0 start conversion 1 x 0 1 start conversion 1 1 0 0 continue conversion 0 x 0 x continue previous operation truth tables mc14549b x = don?t care t?1 = state at previous clock sc sc( t?1 ) eoc clock action x x x none 1 0 0 start conversion x 1 0 continue conversion 0 0 0 continue conversion 0 x 1 retain conversion result 1 x 1 start conversion mc14559b ????????????????????????????????? ????????????????????????????????? (voltages referenced to v ss ) characteristic symbo l v dd vdc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage (note 2) ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 ? 1.2 ? 0.25 ? 0.62 ? 1.8 ? ? ? ? ? 1.0 ? 0.2 ? 0.5 ? 1.5 ? 1.7 ? 0.36 ? 0.9 ? 3.5 ? ? ? ? ? 0.7 ? 0.14 ? 0.35 ? 1.1 ? ? ? ? mad c (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) q outputs (v ol = 1.5 vdc) i ol 5.0 10 15 1.28 3.2 8.4 ? ? ? 1.02 2.6 6.8 1.76 4.5 17.6 ? ? ? 0.72 1.8 4.8 ? ? ? mad c (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) pin 5, 11 only (v ol = 1.5 vdc) 5.0 10 15 0.64 1.6 4.2 ? ? ? 0.51 1.3 3.4 0.88 2.25 8.8 ? ? ? 0.36 0.9 2.4 ? ? ? mad c input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc input capacitance c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) (clock = 0 v, other inputs = v dd or 0 v, i out = 0 a) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current (note 3, 4) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.8 a/khz) f + i dd i t = (1.6 a/khz) f + i dd i t = (2.4 a/khz) f + i dd adc 2. noise immunity specified for worst?case input combination. noise margin for both ?1? and ?0? level = 1.0 v min @ v dd = 5.0 v = 2.0 v min @ v dd = 10 v = 2.5 v min @ v dd = 15 v 3. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + 3.5 x 10 ?3 (c l = 50) v dd f where: i t is in a (per package), c l in pf, v dd in v, and f in khz is input frequency. 4. the formulas given are for the typical characteristics only at 25 c.
mc14549b, mc14559b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (note 5) (c l = 50 pf, t a = 25 c) characteristic symbol v dd min typ max unit output rise time t tlh = (3.0 ns/pf) c l + 30 ns t tlh = (1.5 ns/pf) c l + 15 ns t tlh = (1.1 ns/pf) c l + 10 ns t tlh 5.0 10 15 ? ? ? 180 90 65 360 180 130 ns output fall time t thl = (1.5 ns/pf) c l + 25 ns t thl = (0.75 ns/pf) c l + 12.5 ns t thl = (0.55 ns/pf) c l + 9.5 ns t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time clock to q t plh , t phl = (1.7 ns/pf) c l + 415 ns t plh , t phl = (0.66 ns/pf) c l + 177 ns t plh , t phl = (0.5 ns/pf) c l + 130 ns clock to s out t plh , t phl = (1.7 ns/pf) c l + 665 ns t plh , t phl = (0.66 ns/pf) c l + 277 ns t plh , t phl = (0.5 ns/pf) c l + 195 ns clock to eoc t plh , t phl = (1.7 ns/pf) c l + 215 ns t plh , t phl = (0.66 ns/pf) c l + 97 ns t plh , t phl = (0.5 ns/pf) c l + 75 ns t plh , t phl 5.0 10 15 5.0 10 15 5.0 10 15 ? ? ? ? ? ? ? ? 500 210 155 750 310 220 300 130 100 1000 420 310 1500 620 440 600 260 200 ns sc, d, ff or mr setup time t su 5.0 10 15 250 100 80 125 50 40 ? ? ? ns clock pulse width t wh(cl) 5.0 10 15 700 270 200 350 135 100 ? ? ? ns pulse width ? d, sc, ff or mr t wh 5.0 10 15 500 200 160 250 100 80 ? ? ? ns clock rise and fall time t tlh , t thl 5.0 10 15 ? ? ? ? 15 1.0 0.5 s clock pulse frequency f cl 5.0 10 15 ? ? ? 1.5 3.0 4.0 0.8 1.5 2.0 mhz 5. the formulas given are for the typical characteristics only. ordering information device package shipping ? mc14549bcp pdip?16 25 / rail mc14549bcpg pdip?16 (pb?free) mc14549bdwr2 soic?16 1000 / tape & reel MC14549BDWR2G soic?16 (pb?free) mc14559bcp pdip?16 25 / rail mc14559bcpg pdip?16 (pb?free) mc14559bdwr2 soic?16 1000 / tape & reel mc14559bdwr2g soic?16 (pb?free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc14549b, mc14559b http://onsemi.com 4 switching time test circuit and waveforms 1 f cl t wh(cl) 50% 50% t su t su t su t wh(d) t phl t plh 50% 50% 90% 10% t tlh t plh t thl 90% 50% 10% t tlh s out q7 d sc c note: pin 10 = v ss c l c l c l c l c l c l c l c l c l c l v dd v ss q7 q6 q5 q4 q3 q2 q1 q0 eoc s out c sc ff(mr) d programmable pulse generator timing diagram * ? q8 is ninth?bit of serial information available from 8?bit register. note: pin 10 = v ss inh ? indicates serial out is inhibited low. ? don?t care condition clock sc d q7 q6 q5 q4 q3 q2 q1 q0 eoc s out inh inh q7 q6 q7 q5 q3 q1 q8* inh q6 q4 q2 q0
mc14549b, mc14559b http://onsemi.com 5 operating characteristics both the mc14549b and mc14559b can be operated in either the ?free run? or ?s trobed operation? mode for conversion schemes with any number of bits. reliable cascading and/or recirculating operation can be achieved if the end of convert (eoc) output is used as the controlling function, since with eoc = 0 (and with sc = 1 for mc14549b but either 1 or 0 for mc14559b) no stable state exists under continual cl ocked operation. the mc14559b will automatically recirculate after eoc = 1 during externally strobed operation, provided sc = 1. all data and control inputs for these devices are triggered into the circuit on the positive edge of the clock pulse. operation of the various terminals is as follows: c = clock ? a positive?going transition of the clock is required for data on any input to be strobed into the circuit. sc = start convert ? a conversion sequence is initiated on the positive?going tran sition of the sc input on succeeding clock cycles. d = data in ? data on this input (usually from a comparator in a/d applications ) is also entered into the circuit on a positive?going transition of the clock. this input is schmitt triggered and synchronized to allow fast response and guaranteed quality of serial and parallel data. mr = master reset (mc14549b only) ? resets all output to 0 on positive?going transitions of the clock. if removed while sc = 0, the ci rcuit will remain reset until sc = 1. this allows ea sy cascading of circuits. ff = feed forward (mc14559b only) ? provides register shortening by removing unwanted bits from a system. for operation with less than 8 bits, tie the output following the least significant bit of the circuit to eoc. e.g., for a 6?bit conversion, tie q1 to ff; the part will respond as shown in the timing diagram less two bit time s. not that q1 and q0 will still operate and must be disregarded. for 8?bit operation, ff is tied to v ss . for applications with more than 8 but less than 16 bits, use the basic connections shown in figure 1. the ff input of the mc14559b is used to shorten the setup. tying ff directly to the least significant bit used in the mc14559b allows eoc to provide the cascading signa l, and results in smooth transition of serial informa tion from the mc14559b to the mc14549b. the serial out (s out ) inhibit structure of the mc14559b remains inactive one cycle after eoc goes high, while s out of the mc14549b remains inhibited until the second clock cycle of its operation. q n = data outputs ? after a conversion is initiated the q?s on succeeding cycles go hi gh and are then conditionally reset dependent upon the state of the d input. once conditionally reset they remain in the proper state until the circuit is either reset or reinitiated. eoc = end of convert ? this output goes high on the negative?going transition of the clock following ff = 1 (for the mc14559b) or the conditional reset of q0. this allows settling of the digital circuitry prior to the end of conversion indication. therefore either level or edge triggering can indicate complete conversion. s out = serial out ? transmits conversion in serial fashion. serial data occurs du ring the clock period when the corresponding parallel data bit is conditionally reset. serial out is inhibited on the initial period of a cycle, when the circuit is reset, and on the second cycle after eoc goes high. this provides efficient operation when cascaded. figure 1. 12?bit conversion scheme ?completion of conversion automatically re?initiates cycle in free run mode. ** cascading using eoc guaranteed; no stable unfunctional state. * ff allows eoc to activate as if in 4?stage register. q7 q6 q5 q4 q0 eoc ff sc c d s out mc14559b nc msb to d/a and p arallel data ?? ** * from a/d comparator q7 q6 q5 mr sc c d s out mc14549b lsb q4 q3 q2 q1 q0 eoc to d/a and parallel data external strobe free run mode external clock 1/4 mc14001 serial out (continual update every 13 clock cycles)
mc14549b, mc14559b http://onsemi.com 6 typical applications externally controlled 6?bit adc (figure 2) several features are shown in this application: ? shortening of the register to six bits by feeding the seventh output bit into the ff input. ? continuous conversion, if a continuous signal is applied to sc. ? externally controlled updating (the start pulse must be shorter than the conversion cycle). ? the eoc output indicating that the parallel data are valid and that the serial output is complete. continuously cycling 8?bit adc (figure 3) this adc is running continuously because the eoc signal is fed back to the sc input, immediately initiating a new cycle on the next clock pulse. continuously cycling 12?bit adc (figure 4) because each successive approximation register (sar) has a capability of handling only an eight?bit word, two must be cascaded to make an adc with more than eight bits. when it is necessary to cascade two sar?s, the second sar must have a stable resettable state to remain in while awaiting a subsequent start signal. however, the first stage must not have a stable resettable state while recycling, because during switch?on or due to outside influences, the first stage has entered a reset state, the entire adc will remain in a stable non?functional condition. this 12?bit adc is continuously recycling. the serial as well as the parallel outputs are updated every thirteenth clock pulse. the eoc pulse indicates the completion of the 12?bit conversion cycle, the end of the serial output word, and the validity of the parallel data output. figure 2. externally controlled 6?bit adc to dac sc c s out q7 q6 q5 mc14559b q4 q3 q2 q1 q0 eoc ff figure 3. continuously cycling 8?bit adc to dac sc c s out q7 q6 q5 mc14559b q4 q3 q2 q1 q0 eoc ff
mc14549b, mc14559b http://onsemi.com 7 q7 q6 q5 mr sc c s out mc14549b q4 q3 q2 q1 q0 eoc s out to dac q7 q6 q5 sc cs out mc14559b q4 q3 q2 q1 q0 eoc to dac ff eoc figure 4. continuously cycling 12?bit adc externally controlled 12?bit adc (figure 5) in this circuit the external pulse starts the first sar and simultaneously resets the cascaded second sar. when q4 of the first sar goes high, the second sar starts conversion, and the first one stops conversion. eoc indicates that the parallel data are valid and that the serial output is complete. updating the output data is started with every external control pulse. additional motorola parts for successive approximation adc monolithic digital?to?analog converters ? the mc1408/1508 converter has eight?bit resolution and is available with 6, 7, and 8?bit accuracy. the amplifier?comparator block ? the mc1407/1507 contains a high speed operational amplifier and a high speed comparator with adjustable window. with these two linear parts it is possible to construct sa?adcs with an accuracy of up to eight bits, using as the register one mc14549b or one mc14559b. an additional cmos block will be necessary to generate the clock frequency. additional information on successive approximation adc is found in motorola application note an?716. figure 5. externally controlled 12?bit adc q7 q6 q5 mr sc c s out mc14549b q4 q3 q2 q1 q0 eoc s out to dac q7 q6 q5 sc cs out mc14559b q4 q3 q2 q1 q0 eoc to dac ff eoc
mc14549b, mc14559b http://onsemi.com 8 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ?a? b f c s h g d j l m 16 pl seating 18 9 16 k plane ?t? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip?16 case 648?08 issue t so?16 wb case 751g?03 issue c d 14x b 16x seating plane s a m 0.25 b s t 16 9 8 1 h x 45 m b m 0.25 h 8x e b a e t a1 a l c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not inlcude mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of the b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 10.15 10.45 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 q 0 7
mc14549b, mc14559b http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 mc14549b/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
|
